The number of ECE ILLINOIS' faculty members.
|Digital IC Design||ECE482||G||29966||DIS||1500 - 1550||M W F||2017 ECE Building||Elyse Rosenbaum|
This course is designed to provide senior students with in-depth analysis and design capability required for state-of-the-art digital integrated circuits.
ECE482 is a senior-level elective for electrical engineering and computer engineering majors. This course focuses on the design and analysis of digital integrated circuits. Students are introduced to techniques for designing low-power and high-performance digital integrated circuits in deep submicron CMOS technologies. Topics covered in the course include MOS field effect transistor characteristics, CMOS technology, dc and transient analysis of inverters, combinational logic gates, noise margin, propagation delay, power dissipation, transistor sizing, interconnect properties and buffering, low-power design techniques, bi-stable circuits, latches and registers, dynamic circuits, and semiconductor memories.
A. By the time of Mid-Term I (after 16 lectures), the students should:
3. Understand the mapping from layout to chip cross-section. (a)
4. Be able to calculate the device parasitic capacitances. (a)
5. Be able to calculate the static parameters of the CMOS inverter voltage transfer curve. (a)
6. Be able to employ differential equation-based method as well as approximate methods to calculate the delays of inverters. (a)
7. Understand the sources of power dissipation. (a)
8. Be proficient at using a circuit simulator to study the circuit response. (k)
9. Be able to design combinational logic gates for speed, area or power. (c)
B. After 32 lectures, in addition to the items listed under A, the students should:
11. Be familiar with logic families other than complementary CMOS (e.g., ratioed logic, pass-transistor logic, DCVSL); be able to execute designs using these logic styles; understand the relative advantages and disadvantages of each logic family. (a,c,e)
12. Be able to apply the Elmore delay formula for RC delay calculations (a)
15. Understand timing issues in dynamic circuits (e.g., np-domino, non-footed domino). (a)
17. Understand the use of pipelining to improve circuit throughput. (a)
18. Appreciate and estimate the interconnect parasitics, particular capacitance and resistance. (a)
19. Be able to choose an appropriate load model for delay calculations (lumped C, distributed RC or distributed RLC). (e)
C. At the end of the course, in addition to the items listed under A and B, the students should:
21. Be familiar with low power design techniques. (a)
23. Be familiar with I/O circuits, including high voltage tolerant I/O. (a)
24. Be familiar with the architecture of ROM and RAM circuits. (a)
28. As part of an instructor-assigned team, complete a design project involving the layout, extraction and circuit simulation of a VLSI subsystem (e.g., adder, multiplier) while meeting specifications on throughput and power. Document the design in a written report. (a,c,d,f,g,)