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Achieving Design Correctness (Finally) With Runtime Checking

Speaker Valeria Bertacco, University of Michigan
Date: 12/2/2013
Time: 11:00 am
Location: 141 Coordinated Science Laboratory
Sponsor: Coordinated Science Laboratory
Event Type: Seminar
  Every integrated circuit is released with latent bugs. The damage and risk implied by an escaped bug ranges from almost imperceptible to potential tragedy; unfortunately it is impossible to discern within this range before a bug has been exposed and analyzed. While the past few decades have witnessed significant efforts to improve verification methodology for hardware systems, these efforts have been far outstripped by the massive complexity of modern digital designs, leading to product releases for which an always smaller fraction of system's state has been verified. The news of escaped bugs in large market designs and safety critical domains is alarming because of safety and cost implications (due to replacements, lawsuits, etc.). This talk will present some of our solutions to solve the verification challenge, such that users of future microprocessors can be assured that their devices will operate completely free of bugs. We will attack the problem after deployment in the field, discussing novel solutions which can correct escaped bugs after a system has been shipped.