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DTSTART:20090930T170000
SUMMARY:ECE Explorations (200): "Verification and Validation of Hardware Systems"
DESCRIPTION:<p><strong>Abstract:</strong><br />Modern hardware systems are prone to design errors and bugs that can have very serious consequences. Verification and validation are processes in the design cycle that cause severe bottlenecks in the time to market the chip. This lecture will introduce verification and validation techniques that are used in the state-of-the-art as well as research directions in this field.</p>
<p>Pizza will be served following the presentation!</p>
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LOCATION:151 Everitt Laboratory
UID:20091124T0029173@ece.uiuc.edu
DTSTAMP:20091124T002917
CATEGORY:ECE 200
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