ECE 411
Computer Organization and Design

Section Type Times Days Location Instructor
AB1 LAB -    
AD1 DIS 1400 - 1520 T R   1015 Electrical & Computer Eng Bldg  Rakesh Kumar
Web Page http://courses.engr.illinois.edu/ece411/
Official Description Basic computer organization and design: integer and floating-point computer arithmetic; control unit design; pipelining; system interconnect; memory organization; I/O design; reliability and performance evaluation. Laboratory for computer design implementation, simulation, and layout. Course Information: Prerequisite: ECE 391 or CS 241. Class Schedule Information: Students must register for one lab and one discussion section.
Subject Area Computer Engineering
Course Prerequisites Credit in ECE 391 or CS 241
Course Directors Rakesh Kumar
Detailed Description and Outline

To establish a solid background in computer design and evaluation.

Topics:

  • Introduction and review of logic design
  • Instruction set architectures
  • Computer arithmetic
  • Control unit design
  • Memory organization: memory technologies, memory performance evaluation, interleaved memory, associative memory, virtual memory organization, cache memory
  • Input-Output: devices, controllers, busy wait I/O, channels, interrupts, direct memory access to multiport memory
  • Reliability and performance evaluation
  • Introduction to parallel processing, case studies

Credit is not given toward graduate degrees in Electrical and Computer Engineering.

Computer Usage
The four laboratory projects listed below require using HP PA-RISC workstations and Mentor Design Software to enter and simulate the designs.
Lab Projects
  1. An integer multiplier project
  2. A microprogrammed microprocessor project
  3. A pipelined high performance microprocessor project
  4. A memory management unit with cache project
Topical Prerequisities
  • Combinational and sequential logic design
  • Machine language programming
  • Introduction to Computer Engineering
Texts
D. Paterson and J. Hennessey, Computer Organization and Design: The Hardware/Software Interface.
ABET Category

Engineering Science: 1.5 credits
Engineering Design: 2.5 credits

Course Goals

This course is required for computer engineering majors. The objective of the course is to provide students with a solid foundation in computer design. Through a combination of theoretical framework, practical design techniques, well-defined design problems, open-ended design problems, and teamwork, students develop ability in using design methodology, deriving detailed system descriptions, evaluating feasibility, formulating design problems, being creative in solving design problems, considering alternative solutions, and cooperating with fellow designers to attack demanding assignments. Through report development and formal presentation, students learn to organize, express, promote, and defend their ideas.

Instructional Objectives

A. By the time of exam #1 (after 9 lectures) the students should be able to do the following:

1. Translate a computer design specification into a register transfer language description. (a), (c), (e)

2. Design the data path of a computer from its register transfer language description. (a), (c)

3. Perform performance tuning and extend functionality of a data path design. (a), (c) (e)

4. Design the control unit of a computer using either hardwiring or microprogramming based on its register transfer language description. (a), (c), (e)

5. Implement a simple instruction set computer with a control unit and a data path. (a), (c), (e), (k)

6. Understand implementation issues of more advanced instruction set features such as memory alignment and Endian conventions. (c), (j), (k)

7. Use VHDL to describe the detailed register transfer design at the behavior level (k)

8. Design a basic virtual memory management unit using the concept of one-level and two-level address translation algorithms. (a), (c), (e), (j)

B. By the time of exam #2 (after 17 lectures) the students should be able to do the following:

9. Design a pipelined computer and solve the instruction sequencing, register value forwarding, data interlocking, and precise interrupt problems. (a), (c), (e), (j), (k)

10. Design a basic cache memory with basic organizational techniques and performance tuning. (c), (k)

11. Apply cache design to solve performance problems in other aspects of computer design, e.g., virtual memory address translation (translation lookaside buffer) and pipeline instruction sequencing (branch target buffer). (c), (e), (k)

12. Integrate cache memory with virtual memory management: through virtual-address and physical-address cache memories. (c), (e), (k)

13. Design a bus interconnect for a computer system by addressing timing, arbitration, and locking issues. Understand the concept of more advanced topologies such as point-to-point interconnects and switched networks. (c), (e), (j), (k)

14. Design an I/O subsystem supporting processor programmed I/O, direct memory access, interrupt structures, and industry standards. (c), (e), (j), (k)

15. Understand the concept involved in a floating point unit that supports the IEEE floating-point standard: representable numbers of a format, rounding, underflow, special symbols, and exceptions. (a), (c), (e), (j), (k)

C. By the time of exam #3 (after 28 lectures) the students should be able to do the following:

16. Understand the basic concepts of a multiprocessor design: synchronization and cache coherence protocols. (c), (e), (j), (k)

17. Understand the basic concept of an instruction-level parallel processor design: wide fetch, parallel decode, issue logic, renaming, reservation station, and retirement logic. (j), (k)

18. Understand the basic concepts of explicit instruction-level parallelism: instruction scheduling, very-long-instruction-word computers, explicitly parallel instructions, speculation, prediction. (j), (k)

19. Understand the basic concept of a vector processor design: vector instructions, vector registers, chaining, and vectorization. (c), (e), (j), (k)

Laboratory Objectives

  • The lab assignments are designed to provide solid training in designing modern computers. The first two machine design problems, a simple sequential processor that implements the LC-2 instruction set, is an individual project. This is to ensure that each student learns all the skills required. (c), (e)
  • Students are required to work in pairs on the third machine design problem: a pipelined processor to implement the same LC-2 instruction set. This is to enhance the students' ability to work in teams. (d)
  • The designs are done with state-of-the-art CAD tools. The current environment used is the Mentor design framework with Renoir design capture, VHDL description, and QuickVHDL simulation. This is to give students real-world experience in using design tools. (c), (e), (k)
  • The lab reports are graded according to design correctness, design style, and documentation quality. Points will be taken off with the presence of design errors, unnecessary complications, excessive parts, and vague documentation.
  • This is to ensure that students understand how to clearly document their designs. Students are required to do a face to face demonstration with the teaching assistants to explain their design. (g)
  • The third machine design problem is open-ended. Each team is required to choose an overall approach, identify the control mechanism, implement the data-path, and simulate the entire VHDL design for a pipelined microprocessor. (a), (b), (c), (e), (g), (j), (k)
  • Students are required to consider alternative solutions and justify their design decisions Formal written reports (not to exceed 10 double-spaced pages) and oral presentations are required from each group for this open-ended design problem. Students are asked to attend one of the team presentation sessions in the last two weeks of the course. Each team is allocated fifteen minutes to present and defend their design decisions. This is to ensure that students have gone through a complete design cycle with experience in communicating and defending their design decisions. (e), (g)
Last updated: 2/18/2013