ECE 290
Computer Engineering, I

Displaying course information from Spring 2014.

Section Type Times Days Location Instructor
ADB DIS 0900 - 0950 R   170 Everitt Lab  Jifei Xu
ADC DIS 1000 - 1050 R   163 Everitt Lab  Jifei Xu
ADD DIS 1100 - 1150 R   163 Everitt Lab  Christopher Ryu
ADE DIS 1200 - 1250 R   170 Everitt Lab  Ha Uk Chung
ADF DIS 1300 - 1350 R   170 Everitt Lab  Ha Uk Chung
ADG DIS 1400 - 1450 R   170 Everitt Lab  Chunan Wei
ADH DIS 1500 - 1550 R   170 Everitt Lab  Vinay Maddali
AL1 LEC 1200 - 1250 M W   112 Chemistry Annex  Donna Brown
AL2 LEC 0900 - 0950 M W   103 Talbot Laboratory  Volodymyr Kindratenko

Web Page
Official Description Digital logic and computer systems. Representation of information; combinational network analysis and design; sequential network analysis and design; computer organization and control. Laboratory for design and simulation of digital systems. Course Information: Credit is not given for both ECE 290 and CS 231. Prerequisite: Credit or concurrent registration in ECE 190. Class Schedule Information: Students must register for one discussion and one lecture section.
Subject Area Computer Engineering
Course Prerequisites Credit or concurrent registration in ECE 190
Course Directors Zbigniew T Kalbarczyk
Detailed Description and Outline

An understanding of the working of digital systems, including computer organization at the functional and logical levels.


  • Representation of information.
  • Switching algebra.
  • Combinational network analysis and design.
  • Sequential network analysis and design.
  • Binary arithmetic and arithmetic-logic unit.
  • Computer organization and machine-level programming.
  • Input-output.
  • Control and design.

Credit is not given for both ECE 290 and CS 231.

Computer Usage
There are assignments each week on UNIX graphic workstations running a commercial CAD System. Half of the assignments utilize schematic capture and simulation software to teach combinational and sequential logic design concepts.
Mano & Kime, Logic and Computer Design Fundamentals, Prentice-Hall, 1997
ABET Category
Engineering Science: 67%
Engineering Design: 33%
Course Goals

ECE 290 is required for undergraduates in both electrical engineering and computer engineering curricula. The overall goals of the course are

  • To design and analyze combinational and sequential logic networks.
  • To understand the principles of computer organization.
  • To develop the skills required to solve engineering problems.
  • To develop an appreciation for ethical responsibilities faced by practicing engineers.

By the end of ECE 290, students understand how computers execute instructions, and they are able to design the hardware of a computer.

Instructional Objectives

Representation of information

  • Convert between decimal, binary, octal, and hexadecimal representations of integers (a)
  • Distinguish between a variety of decimal and alphanumeric codes (a)
  • Understand Hamming distance and Hamming codes (a)
  • Determine the number of errors that a code can detect or correct (a)
  • Understand two’s complement representation of integers and determine whether overflow occurs in arithmetic operations (a)
Design and analysis of combinational networks
  • Understand the operation of discrete logic gates (a)
  • Analyze a combinational network using Boolean expressions (a)
  • Convert a verbal specification into a Boolean expression (c, e)
  • Understand basic properties of Boolean algebra: duality, complements, standard forms (n)
  • Apply Boolean algebra to prove identities and simplify expressions (a, e)
  • Use Karnaugh maps to find minimal sum-of-products and products-of-sums expressions (e)
  • Design combinational networks that use NAND, NOR, and XOR gates (c, e)
  • Design with MSI components such as encoders, decoders, multiplexers, adders, arithmetic-logic units, ROMs, and programmable logic arrays (c, e)
  • Calculate delays in ripple carry adders and combinational arrays (a)
  • Understand fast adder circuits, including carry-lookahead (a, c)
Design and analysis of sequential networks
  • Understand the operation of latches; clocked, master-slave, and edge-triggered flip-flops; shift registers; and counters (a)
  • Plot and interpret timing diagrams (a, b)
  • Determine the functionality of sequential circuits from state diagrams and timing diagrams (a, b)
  • Translate sequential circuit specifications into state diagrams (c, e)
  • Design sequential circuit components (latches, flip-flops, registers, synchronous counters) using logic gates (c, e)
  • Synthesize general sequential circuits (c, e)
  • Understand tradeoffs in register and counter design (c)
Computer organization
  • Understand the operation of tri-state buffers and their uses in multiplexing outputs and enabling bi-directional signaling (a)
  • Understand the operation of random access memories (a)
  • Synthesize a large memory from smaller memories and decoders (c, e)
  • Design datapath components, including register files, buses, and functional units (c, e)
  • Design a hardwired control unit to implement an instruction set (c, e)
  • Design a microprogrammed control unit to implement an instruction set (c, e)
  • Understand tradeoffs between hardwired and microprogrammed control (c)
  • Understand instruction formats and addressing modes (a)
  • Understand the operation of stack instructions, control flow, and interrupts (a)
  • Specify new instructions and addressing modes in register transfer language (c, e)
  • Translate register transfer language statements into microcode (e)
  • Analyze the effects of individual instructions and machine-level programs (a)
  • Write short machine-level programs (c, e)

Ethics and professionalism

  • Familiarity with engineering codes of conduct, such as IEEE and ACM (f, h)
  • Through (fictional and real) case studies, evaluate behaviors with respect to ethical standards (f, g, i, j)
  • Study an actual catastrophic event and evaluate the causes and impact (f, g, h, i)
  • Communicate effectively in writing (f, g)
Laboratory skills
  • Use professional CAD software on engineering workstations for schematic capture and simulation of small digital systems (b, k)
  • Simulate adder delays and carry-lookahead adders (b,k)

Last updated: 2/15/2013