ECE 482
Digital IC Design

Section Type Times Days Location Instructor
G DIS 1500 - 1550 M W F   2017 ECE Building  Elyse Rosenbaum
Web Page
Official Description Bipolar and MOS field effect transistor characteristics; VLSI fabrication techniques for MOS and bipolar circuits; calculation of circuit parameters from the process parameters; design of VLSI circuits such as logic, memories, charge-coupled devices, and A/D and D/A converters. Course Information: 3 undergraduate hours. 3 graduate hours. Prerequisite: ECE 290 and ECE 342.
Subject Area Integrated Circuits and Systems
Course Prerequisites Credit in ECE 290
Credit in ECE 342
Course Directors Naresh R Shanbhag
Detailed Description and Outline

This course is designed to provide senior students with in-depth analysis and design capability required for state-of-the-art digital integrated circuits.


  • Basic theory and characteristics of MOS devices
  • Circuit models and computer-aided analysis of MOS circuits
  • Design of the basic MOS digital inverter
  • Design with MOS static and dynamic circuits
  • MOS memories
  • Programmable logic arrays
  • I/O circuit design
  • BICMOS circuits
Computer Usage
Weekly homework assignments include use of SPICE program for transient and dc analysis of digital integrated circuits.
Topical Prerequisities
  • Semiconductor materials and their electronic properties
  • Electronic circuit analysis
  • Digital logic circuits
J. M. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits, 2nd ed., Prentice-Hall.
ABET Category
Engineering Science: 1 credit or 33%
Engineering Design: 2 credits or 67%
Course Goals

ECE482 is a senior-level elective for electrical engineering and computer engineering majors. This course focuses on the design and analysis of digital integrated circuits. Students are introduced to techniques for designing low-power and high-performance digital integrated circuits in deep submicron CMOS technologies. Topics covered in the course include MOS field effect transistor characteristics, CMOS technology, dc and transient analysis of inverters, combinational logic gates, noise margin, propagation delay, power dissipation, transistor sizing, interconnect properties and buffering, low-power design techniques, bi-stable circuits, latches and registers, dynamic circuits, and semiconductor memories.

Instructional Objectives

A. By the time of Mid-Term I (after 16 lectures), the students should:

1. Be familiar with the I-V characteristics of deep-submicron MOSFETs. (a,j)

2. Understand the limited validity of simple I-V MOS models and be able to extract model parameters. (a,b)

3. Understand the mapping from layout to chip cross-section. (a)

4. Be able to calculate the device parasitic capacitances. (a)

5. Be able to calculate the static parameters of the CMOS inverter voltage transfer curve. (a)

6. Be able to employ differential equation-based method as well as approximate methods to calculate the delays of inverters. (a)

7. Understand the sources of power dissipation. (a)

8. Be proficient at using a circuit simulator to study the circuit response. (k)

9. Be able to design combinational logic gates for speed, area or power. (c)

10. Be able to use transistor sizing techniques for minimizing delay through a single combinational logic gate or a chain of logic gates. (a,c,e)

B. After 32 lectures, in addition to the items listed under A, the students should:

11. Be familiar with logic families other than complementary CMOS (e.g., ratioed logic, pass-transistor logic, DCVSL); be able to execute designs using these logic styles; understand the relative advantages and disadvantages of each logic family. (a,c,e)

12. Be able to apply the Elmore delay formula for RC delay calculations (a)

13. Be able to design dynamic logic gates. (a,c)

14. Be familiar with techniques for improving data integrity in dynamic gates.(a,b,c)

15. Understand timing issues in dynamic circuits (e.g., np-domino, non-footed domino). (a)

16. Be able to analyze and design static and dynamic latches and registers. (a,c,e)

17. Understand the use of pipelining to improve circuit throughput. (a)

18. Appreciate and estimate the interconnect parasitics, particular capacitance and resistance. (a)

19. Be able to choose an appropriate load model for delay calculations (lumped C, distributed RC or distributed RLC). (e)

20. Be proficient at buffer insertion and sizing for interconnect delay reduction. (a,c)

C. At the end of the course, in addition to the items listed under A and B, the students should:

21. Be familiar with low power design techniques. (a)

22. Appreciate the many different ways of implementing a functional block, such as an adder. (a,c)

23. Be familiar with I/O circuits, including high voltage tolerant I/O. (a)

24. Be familiar with the architecture of ROM and RAM circuits. (a)

25. Be able to design a memory array decoder. (a,c)

26. Be able to analyze and design an SRAM memory cell. (a,b,c,e)

27. Be able to analyze the operation of a DRAM memory cell. (a,e)

28. As part of an instructor-assigned team, complete a design project involving the layout, extraction and circuit simulation of a VLSI subsystem (e.g., adder, multiplier) while meeting specifications on throughput and power. Document the design in a written report. (a,c,d,f,g,)

Last updated: 5/23/2013