ECE 483
Analog IC Design

Displaying course information from Spring 2014.

Section Type Times Days Location Instructor
L DIS 1400 - 1520 T R   106B8 Engineering Hall  Pavan Kumar Hanumolu
Web Page
Official Description Basic linear integrated circuit design techniques using bi-polar, JFET, and MOS technologies; operational amplifiers; wide-band feedback amplifiers; sinusoidal and relaxation oscillators; electric circuit noise; application of linear integrated circuits. Course Information: 3 undergraduate hours. 3 graduate hours. Prerequisite: ECE 342.
Subject Area Integrated Circuits and Systems
Course Prerequisites Credit in ECE 342
Course Directors Pavan Kumar Hanumolu
Detailed Description and Outline

To teach Electrical Engineering seniors basic analog IC design skills.


  • Large and small signal analysis
  • Op amp design
  • Closed-loop stability of op amp
  • Electric circuit noise
  • Feedback amplifiers
  • Oscillator
Computer Usage

Using SPICE to simulate ac and transient responses of analog circuits for the homework; high-performance op-amp design for the term project.

Topical Prerequisities
  • Bipolar and MOS device physics
  • Basic circuit theory; KCL, KVL, Laplace transform, and Bode plot
  • Feedback stability criteria; magnitude and phase margin
  • Circuit simulation program; SPICE

Gray, Hurst, Lewis and Meyer, Analysis & Design of Analog ICs, 4th ed., Wiley, 2001.

ABET Category

Engineering Science: 2 credits or 67%
Engineering Design: 1 credit or 33%

Course Goals

This course is a senior elective for electrical engineering majors. The goals are to introduce basic transistor circuit design concepts using bipolar and CMOS, to give students practical design experience with design examples and to make electrical engineering majors ready for analog integrated circuit design tasks.

Instructional Objectives

A. By the time of Midterm Exam (after about 20 lectures), the students should be able to do the following:

1. Understand the large and small signals and use bipolar and MOS transistor models. (a,m)

2. Estimate driving-point small-signal resistance using four resistance reflection rules. (a,k,m)

3. Identify three basic amplifier configurations: common emitter (source), common base (gate) and common collector (drain). Handle bipolar and MOS transistors with emitter (source) degeneration. (a,k,m)

4. Understand and estimate the gain and input/output resistances of two-stage amplifiers from nine possible combinations. (a,k,m)

5. Use two-stage amplifier configurations and understand the differential pair and its offsets and common-mode rejection. (a,m)

6. Design current sources and mirrors for integrated circuits including such sophisticated topics as supply- and temperature-independent biasing circuits. (c,k)

7. Design a band-gap reference generator. (c,k)

8. Perform DC and AC analysis of the standard operational amplifier and understand high performance operational amplifier design for low offset, low input current and low offset drift. (a,k,m)

B. By the time of Final Exam (after 42 lectures), the students should be able to do all of the items listed under A and B, plus the following:

9. Understand the gain-bandwidth concept and frequency response of the three basic amplifiers. (a,m)

10. Estimate dominant pole frequencies using pole splitting Miller effect and the zero-value time constant method. Extend the concepts to understand the frequency response of operational amplifiers. (a,k,m)

11. Apply the Nyquist stability and use the Bode plot to estimate the phase margin of operational amplifiers in feedback. Understand operational amplifier frequency compensation. (a,k,m)

12. Estimate the transient settling time of amplifiers and understand the slewing and settling behaviors. (a,k,m)

13. Design high-performance operational amplifiers with high slew rates and understand other variations in the operational amplifier design in both CMOS and bipolar technologies. (c,k)

14. Identify circuit noise sources from active and passive devices and handle noise power spectral density. (a,m)

15. Estimate circuit noise density, minimum detectable signal and noise figure. (k)

Last updated: 9/22/2014