ECE 512
Computer Microarchitecture

Displaying course information from Spring 2009.

Section Type Times Days Location Instructor
G LCD 1400 - 1520 T R   170 Everitt Lab  Matthew Frank
Web Page
Official Description Design of high performance computer systems; instruction level concurrency; memory system implementation; pipelining, superscalar, and vector processing; compiler back-end code optimization; profile assisted code transformations; code generation and machine dependent code optimization; cache memory design for multiprocessors; synchronization implementation in multiprocessors; compatibility issues; technology factors; state-of-the-art commercial systems. Course Information: Prerequisite: ECE 511 and CS 426.
Subject Area Hardware Systems
Course Prerequisites Credit in ECE 511
Credit in CS 426
Course Directors Wen-Mei W Hwu
Detailed Description and Outline


  • Introduction and architecture
  • Retargetable optimizing code generators
  • Compile-time instruction memory access optimization: inlining and trace placement
  • Instruction sequencing: branch target buffers, slot-based methods, exception handling, complexity and efficiency
  • Data register efficiency: register allocation, renaming, windowing, interprocedural allocation
  • Instruction concurrency: interlocking, forwarding compaction, multiple issue, state recovery
  • Execution efficiency: hyperblock global code transformation
  • Caches and interconnection for multiprocessors: directory/snooping nvalidate/update, multilevel, compilation, bus architectures
  • Synchronization for multiprocessors: atomicity and locii, processor chips, processor boards, buses and memory boards
  • Advanced system design tools: benchmark characterization, execution driven simulation, and fast system simulation

Same as CSE 528.

Lecture notes and collection of technical papers.
Last updated: 2/13/2013