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Contact Info

William H. Sanders
Department Head
ECE ILLINOIS
306 N. Wright Street
Urbana, IL 61801
Ph: (217) 333-2300
Fax: (217) 244-7075
whs@illinois.edu

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Jose E. Schutt-Aine

Electrical and Computer Engineering
Jose E. Schutt-Aine
Jose E. Schutt-Aine
Professor
5042 ECE Building
306 North Wright Street
Urbana Illinois 61801
(217) 244-7279

Primary Research Area

  • Circuits

Education

PhD Electrical & Computer Engineering University of Illinois May 1988

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Research Statement

The era of big data will lead to systems necessitating the transport of large amounts of information. Today's high-speed I/O signaling links are faced with difficult challenges: pins and interconnects available for off-chip signaling remain almost constant, while the throughput needed is increasing and the required aggregate bandwidths are moving into the Tb/s range (with target bit error rates as low as 10-21 for memory links).

High-speed chip-to-chip communication has historically been considered less critical than the on-chip signaling performance; however, due to today's huge demands for data throughput, off-chip interconnect bandwidth is increasingly becoming the system bottleneck, and creative solutions are needed to meet the requirements, now measured even in terabytes per second for graphic processing cores. Due to manufacturing and technology limitations, the physical dimension scaling of the passive package and interconnect systems is unable to keep up with the rapid miniaturization benefits enjoyed by active devices (such as silicon chips in CMOS technology nodes) which is dictated by Moore's law. Therefore, the resources (pins and interconnects) available for off-chip signaling remain almost constant, while the throughput needed is increasing. This trend is expected to persist in the future. At the same time, in order to keep up with the data throughput needed over limited resources, high edge rates are being used for signaling. This causes various signal integrity impairments, which in turn limit the system performance and force the data rates to be well below the Shannon limit of the channel capacity. Coupled with the limited channel resources are the conflicting requirements of low power and extremely reliable signaling . All of these limitations combined call for creative solutions in order to keep up with the performance demands of next-generation systems.

In our research group we investigate how these changes will affect the different aspects of high-speed link design. We develop modeling and simulation strategies as well as techniques for mitigating noise while reducing power.

Research Interests

High-Frequency Measurements, Mixed-Signal Design, High-Performance Computing for Electromagnetic Modeling, CAD Tools for Interconnects and Packages, Signal Integrity,

Research Areas

Honors

  • Certificate of Honor, IEEE CPMT, Bangalore Chapter, India, December 2005
  • 2000 UIUC-NCSA Faculty Fellow
  • 1998 CPMT-IEEE Education Award
  • NSF MCAA Award, 1996
  • 1994 Advisor's List for Advising Excellence, Spring 1994
  • NASA Faculty Award for Research, 1992
  • NSF MRI Award, 1991
  • Incomplete List of Teachers Ranked as Excellent by their Students, Fall 1988

Teaching Honors

  • 1998 CPMT-IEEE Education Award
  • 1994 Advisor's List for advising excellence, Spring 1994
  • Incomplete List of Teachers Ranked as Excellent by their Students - Spring 1988, Fall 1988