Primary Research Area
- Hardware systems
University of California, San Diego. Ph.D in Computer Engineering. Department of Computer Science & Engineering. September 2006.
Rakesh Kumar is an Associate Professor in the Electrical and Computer Engineering Department at the University of Illinois at Urbana Champaign. His current research interests are in stochastic computing, low power and error resilient computer systems, and architectures for inference and machine learning. His past research on single-ISA heterogeneous multi-core architecture and conjoined-core architectures has directly influenced processor products and roadmaps from several companies. His research recognitions include several best paper awards and best paper award nominations, ARO Young Investigator Award, Arnold O Beckman Research Award, FAA Creative Research Award, UCSD CSE Best Dissertation Award, and an IBM PhD Fellowship. Teaching recognitions include appearance on UIUC's List of Teachers Ranked as Excellent. Rakesh has a BS from IIT Kharagpur and a PhD from University of California at San Diego.
University of Illinois, Urbana-Champaign, Department of Electrical and Computer Engineering. Assistant Professor, Jan 2007-August 2013.
For more information
Passat Group at UIUC is looking at Programmable, Adaptable, and Scalable Systems, Architectures, and Technologies. Specifically, we are interested in robust and low power processors and systems with focus on a) scalability: ability to seamlessly exploit multiple levels of concurrency in workloads, b) adaptability: proactive and reactive adjustment to workload types, application requirements, compute conditions, and objective functions, and c) programmability: cooperative information exchange between hardware and software for productivity and efficiency.
Our work spans all layers of the computing stack - circuits, architectures, compilers, systems, and applications. A typical member of the PASSAT group is creative, hardworking, motivated, and ambitious. He/she has strong programming skills, with a background in circuits, CAD, or computer architecture. He/she is open to learning new skills and considers hard problems as particularly interesting. Students who do not fit the above profile are, in general, not good fits.
The current flagship project of the PASSAT group is computing with stochastic processors (or processors that do not always compute correctly by design). Please refer to the project pages for details.
Passat Group is led by Dr Rakesh Kumar.
Undergraduate Research Opportunities
I am looking for motivated undergraduate students to join my group. Email email@example.com if you want to do research in computer architecture, reconfigurable computing, or hardware/software interface. See our research/publications pages (http://passat.crhc.uiuc.edu) for a sampling of our research. Please attach your CV as well.
- Fault tolerance, reliability
- Low power and complexity-effective designs
- CAD/architecture interactions
- Computer Architecture
- Algorithms and computational complexity
- Computer aided design
- Computer aided design of integrated circuits
- Computer architecture
- Fault tolerance and reliability
- Hardware systems
- Integrated circuit reliability
- Logic design and VLSI
- Machine learning
- Machine learning and pattern recognition
- Parallel processing
- Robotics and motion planning
- List of Teachers Ranked as Excellent. Spring 2013.
- Invited Visiting Lecturer. The 4th International Summer School on Computer Science. School of Computer, National University of Defense Technology (NUDT). China. July 2011.
- Best of IEEE Computer Architecture Letters. 2014.
- Keynote Speaker. The Workshop on Stochastic Modelling and Computing for Weather and Climate Prediction. March, 2013.
- Keynote Speaker. The 7th Workshop on Compiler Assisted SoC Assembly (CASA). 2012.
- ARO Young Investigator Award, 2012
- Best Paper Award Nomination. The 18th International Symposium on High Performance Computer Architecture (HPCA), 2012.
- Keynote Speaker. The 2nd Workshop on Resilient Architectures(WRA). 2011.
- Best Paper Award. International Conference on Compilers, Architectures, and Synthesis of Embedded Systems (CASES). 2011.
- Best Paper in Session Award. SRC TECHCON. 2011.
- Keynote Speaker. The 5th Workshop on Dependable and Secure Nanocomputing (WSDN). 2011.
- Keynote Speaker. The 4th IEEE Workshop on Low Power Design Impact on Test and Reliability. 2011.
- Arnold O Beckman Research Award, 2009
- FAA Creative Research Award, 2008
- UC San Diego CSE Dissertation Award, 2007. Nominated for ACM Distinguished Dissertation Award.
- IBM PhD Fellowship, 2005-2006
- Jagdish Bose National Science Talent Search (JBNSTS) scholarship, 1997-2001
Public Service Honors
- Guest Editor, Computer Architecture News, March 2009, March 2008, March 2007, November 2005
- Co-founder and Workshop Co-chair. Workshop on Design, Architecture, and Simulation of Chip Multiprocessors (dasCMP), 2005-2008.
- Guest Editor, Special Issue on Reliable Embedded Computing, IEEE Embedded Systems Letters, September 2010.
- General Chair. The 7th IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE). Urbana. March 2011.
- Guest Editor. Special Issue on New Software/Hardware Paradigms for Error-tolerant Multimedia Systems. IEEE Transactions on Multimedia. 2012.
- General Chair. The 8th IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE). Urbana. March 2012.