Ph.D., Electrical Engineering, University of California, Berkeley, Dec. 1992
Elyse Rosenbaum received the B.S. degree (with distinction) from Cornell University in 1984, the M.S. degree from Stanford University in 1985, and the Ph.D. degree from the University of California, Berkeley in 1992. All of these degrees were in electrical engineering. From 1984 through 1987, she was a Member of Technical Staff at AT&T Bell Laboratories in Holmdel, NJ. She is currently a Professor in the Department of Electrical and Computer Engineering at the University of Illinois at Urbana-Champaign.
Dr. Rosenbaum’s present research interests include design, testing, modeling and simulation of on-chip ESD protection circuits, CDM-ESD reliability of stacked packaging and 3D-IC, design of high-speed I/O circuits, latch-up, gate dielectric degradation, and system-level ESD reliability. She has authored or co-authored well over 100 technical papers. She has presented tutorials on reliability physics at the International Reliability Physics Symposium, the EOS/ESD Symposium, and the RFIC Symposium. She was the keynote lecturer at the 2004 Taiwan ESD Conference, and has given invited lectures at many universities and industrial laboratories. From 2001 through 2011 she was an editor for IEEE Transactions on Device and Materials Reliability. She is currently an editor for IEEE Transactions on Electron Devices.
Dr. Rosenbaum has been a visiting professor at Katholieke Universiteit in Leuven, Belgium and National Chiao-Tung University in Hsinchu, Taiwan. She has been the recipient of a Best Student Paper Award from the IEDM, an Outstanding Paper Award from the EOS/ESD Symposium, a Technical Excellence Award from the SRC, an NSF CAREER award, an IBM Faculty Award, and a UIUC Bliss Faculty Scholar Award. She is a Fellow of the IEEE.
Graduate Research Opportunities
Research opportunities exist for students with interests in device physics, circuit design and electromagnetics. Students must have good communication skills and an electrical engineering background.
System-level ESD reliability ESD-robust high-speed I/O circuit design Soft error mitigation CDM-ESD protection for System-in-Package and System-on-Chip Compact modeling of on-chip ESD protection devices Efficient simulation of IC CDM reliability Transient latch-up Gate dielectric reliability ESD reliability of 3D-ICs
IEEE Fellow for "contributions to electrostatic discharge reliability of integrated circuits," 2011