LED ARRAY 20 horizontal by 14 vertical

Each Column and Row is driven by a 74LS244 buffer's output.

To turn on a Row, Ground the input on the 74LS244.

To turn on a Column, apply +5VDC to the input on the74LS244.

You must rapidly multiplex the inputs to obtain the display you want.

KEYPAD sixteen keys 0-9, A-D,#,*.

You will need a 74C922 Keypad decoder to convert the 4 row and 4 column lines into 4 bit BCD.

The +5VDC supply is protected by a 5 watt zener diode.

Computer Programmable Logic Device (CPLD)

MACH111SP and MACH211SP Chip Datasheets

We HIGHLY RECOMMEND that you design a very simple circuit and test that you can program the CPLD

BEFORE you spend a lot of time designing your complicated circuit.

You can use the following files to test your chip.

Right Click on the file you want and then "Save Target As...."

Inverters.syn The ispDesignEXPERT(tm) Starter file.

Inverters.sch The Schematic.

Inverters.jed The JED file to be donwloaded to the chip.

Since the Mach211 has 32 I/O pins, there are 16 inverters.

All even I/O pin numbers are the inverter inputs and all odd I/O pin numbers are inverter outputs.

ispDesignEXPERT-Starter Overview

The ispDesignEXPERT(tm) Starter software version 8.1 includes support for the design of ispLSI, ispMACH, MACH, GAL and PAL devices up to 600 macrocells. For the first time, VHDL and Verilog Synthesis by Synplicity has been added to the Starter Software package. This package also includes ABEL and Schematic Entry, Device Fitting, Timing Analysis and Functional Simulation. EDA Interface Kits are available to support device design from within your existing environment.

Download ispDesignEXPERT-Starter software from Lattice.

Programming Lattice CPLD,

For Schematic Capture, a cookbook approach

by James Wehmer

(For more details see ispDesignExpert Project Navigator; Help; Tutorial.)

Start ispDesignExpert CPLD Project Navigator Software

Double click on the ispDesignExpert icon

Begin a new project

(if you want to continue working on an existing project, select FILE; Open Project.)

Select FILE; NEW PROJECT (this opens a “Create New Project” window)

Change Project Filename: from Untitled to yourfilename.syn SAVE

Back in Project Navigator, Double click on “Untitled” and rename it yourfilename. OK

Click on “New” at the bottom of the window. OK

In the New Source Window, select Schematic. OK

Enter the name for a New Schematic,yourfilename.sch. SAVE

You should now have a Schematic Editor new window appear.

Select the chip type.

In the Project Navigator window, double click on ispLSI5384V-125LB388.

This will bring up a “Device Selector” window.

Select Family = MACH 1 or 2; Device; Speed Grade; Package type, and Part Name. OK, YES, YES

Design your circuit. In the Schematic Editor window

(To work on an existing schematic, double click on yourfilename.sch in the Project Navigator window.)

Select ADD; SYMBOL, Choose a symbol from one of the libraries and place it on the schematic.

For PLD chip INPUTS use IOPADS.LIB; G_INPUT (you only get 32-I/O pins max.)

For PLD chip OUTPUTS use IOPADS.LIB; G_OUTPUT

For various Logic Gates use GATES.LIB:

Select ADD; Net Name, type in a label for the I/O signal, and place it next to the G_INPUT or G_OUTPUT.

Select ADD; I/O Marker, choose either input or output, and click on the Net Name you placed in the previous step.

Select ADD; WIRE, to connect your symbols together.

Select EDIT; Attribute; Symbol Attribute, and click on a G_INPUT or G_OUTPUT symbol.

In the Symbol Attribute Editor window, select Synario Pin =*.

In the upper right box, type in the chip I/O pin number that you want this signal to go on.

Select another G_INPUT or G_OUTPUT symbol.

You can use EDIT;--- to Delete, Move, or Copy symbols and lines.

FILE; SAVE

To build a multiplexer;

ADD; 4 to 1 MUX

ADD; symbol; MUXES.LIB; G_MUX41

Compile Yourfilename.JED file.

In the Project Navigator window, select Tools; Import Source Constraint Options

Check the box Import Constraints From Design Source OK

In the Project Navigator window, select Tools; Ignore Project Assignments

Make sure that there are NO boxes checked in any of the three windows CLOSE

In the Project Navigator window, Select MACH*11-****, and double click on “Fit Design” Process.

When this process completes, you should get a green check mark next to “JEDEC File”.

In the Project Navigator window, double click on “Post-fit Pinout” .

Verify that the pins are the ones that you wanted

Download *.JED file to your chip.

Connect a special supplied programming cable from the PC LPT1: parallel printer port to

the 10 pin IDC connection on the PLD-Keypad-LED circuit board.

In the Project Navigator window, select Tools; Lattice/VantisPRO Software

JETAG Chain Editor and MACH Programmer Software

Select FILE; NEW

Select PROJECT; ADVANCED OPTIONS; Use Vantis Cable.

Select EDIT; ADD DEVICE

In the JTAG Part Properties window that appears, enter------

Part description anything

Part name your CPLD chip number

JTAG Operation P = Erase, Program & Verify Device w/ JEDEC File

JEDEC File yourfilename.JED in the same directory as your schematic file.

In the JETAG Chain Editor and MACH Programmer Window, click on the green “GO” button.

Overwrite? OK

You should now see your chip being programmed---

Device Being Processed : (mach*** )

Programming Row 60 - 0

Reading Row 60 - 0

== > No Errors

Continue

JTAG Processing Complete OK

If you get any error messages, it is probably because;

1) +5VDC to CPLD is low.

2) The programming cable is not connected.

3) Your “Get File” above is not in the directory C:\VANTIS\WMACHPRO\yourfilename.JED

4) Your CPLD chip is not installed properly into the chip socket.

5) You found a new way to mess up.