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William H. Sanders
Interim Department Head
ECE ILLINOIS
1406 W. Green St.
Urbana, IL 61801-2918
Ph: (217) 333-2300
Fax: (217) 244-7075
whs@illinois.edu

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ECE Electronics Service Shop

Design Requirements For Our Milled PCBs

Vias And Pads Will Not Be Plated Through

Due to the nature of the milling process, the vias and pads are not plated through the board, meaning the top and bottom sides are not initially connected. This has important consequences:

  1. For a via to connect from the top to the bottom, you must insert a wire and solder it on both the top and bottom sides.

  2. If you run a trace on the top layer to a component's pin, you must solder the pin on the top side of the board for a reliable connection. This is not always possible. See "Traces To Component Pins On The Top Layer" below.

Trace Dimensions

Big wide traces are good, up to a point. You should make the traces as wide as possible given the density of the circuit. That makes the board much easier for me to mill and much easier for you to solder.

To make a group of traces wider in Eagle:

  1. Use Group to select a group of objects containing the desired traces.
  2. Do Change...Width...and select the desired width. .024" or .032" is good if you have room.
  3. Right-click on the selected group of traces. They should all get wider.
  4. Move any trace that has become too close to something now. If the trace must be narrow because there's no room to move it, change the width of it back. Do Change...Width...select the narrower width, and LEFT click on the trace.

These images give a general idea of what trace widths will work when running traces between pins:

Too Narrow

Too Wide

Just Right


If your board absolutely requires narrow traces, then use trace width >= 10 mil (10 mil = 1/100 inch = 0.254 mm). Separate tracks, pads, vias, etc. by spaces >= 10 mils wide.




Ground Planes or Fill Areas

In Eagle you use the "Polygon" command to create areas of solid copper on the board. Unless you are using the background copper as a ground or power plane, please do not submit boards with polygons drawn over the whole board. In the past, some students have gotten the impression that we will always remove all copper from the board that is not shown as copper in their files. They will then put polygons on the board not connected to ground or power to prevent it all from being removed, like this:


We would rather you submit a design like this:

Then, unless you specify otherwise, we will only remove a 1mm insulation channel around the outside of your traces, like this:

We can manufacture the boards more quickly if we define those empty channels rather than you.

But in cases where the background copper is to be used as a ground or power plane, use the Polygon function.

We often receive board submissions with Polygon areas that look like this, in which the Polygon's "Isolate" parameter is set to 8 mil = 0.008":




It is much better if you increase the "Isolate" parameter on your Polygon to something like 50 mil, producing something more like this:




This makes is a lot easier for us to fabricate the board and for you to solder on it without accidentally shorting pins to the background copper.





Trace Current Capacity

A common mistake is to make traces that are too narrow to handle the necessary current. These burn up spectacularly the first time you turn on the power, like this:



More current requires wider traces. Our FR4 board material has "1 ounce" copper on both sides, so your traces will be made of this. The chart below shows the trace temperaures that will occur for different currents on 1 ounce traces of different widths. Use it as your guide for trace width.

Temp Rise 10°C 20°C 30°C
Trace Width in Mil Maximum Current in Amps
10 1.0 1.2 1.5
15 1.2 1.3 1.6
20 1.3 1.7 12.4
25 1.7 2.2 2.8
30 1.9 2.5 3.2
50 2.6 3.6 4.4
75 3.5 4.5 6.0
100 4.2 6.0 7.5
200 7.0 10.0 13.0
250 8.3 12.3 15.0


You can also use this PCB Trace Width Calculator.




No Vias (aka Feedthroughs) Under Surface Mount ICs

As discussed above, you must solder wires into all vias. These solder joints create a small bump on the board. If the bump is underneath a surface mount IC, it may be impossible to solder the IC down. So do not put vias under these chips.

BAD GOOD


If you are using the autorouter in Eagle, restricted zones can be defined to prevent placement of vias under these chips. These are defined by drawing shapes on the "vRestrict" layer. In my PDF Eagle manual, this is described on page 143. Your manual page may vary.

Having vias underneath socketed DIP ICs is usually not a problem.


Eagle Autorouter Parameters and Design Rules

The not-so-great Autorouter function in Eagle can create absurdly complex routings with dozens or HUNDREDS of vias. Remember that you will have to solder a wire into each one, so you want to minimize the number. I recommend routing the board by hand if at all possible for a better design.

If you must use the Autorouter function in Eagle, then download this ZIP file and use the Autorouter Parameter and Design Rules files contained in it. Please DO NOT use the default Design Rules and Autorouter settings in Eagle. They will produce boards that are very difficult for me to make due to the very narrow traces and close spacing.

Instructions for using my files in Eagle Version 4.16r2:

  1. Extract the files from the above ZIP file into a convenient directory.
  2. In the Board editor click on the "DRC" icon to bring up the Design Rules dialog.
  3. Hit the "Load" button and select "MWSEagleDesignRules.dru".
  4. Close the Design Rules dialog.
  5. Click on the Auto icon to bring up the Autorouter Setup dialog.
  6. Hit the "Load" button and select "MWSEagleAutorouterParams.ctl".
  7. You can now Autoroute a board which will not cause me severe headaches.

Defining The Board Outline In Eagle

When defining the outline of the board on the Dimension layer, please draw it with wires with width=0. This is especially important if you want traces to go right up to the edge of the board. Width=0 makes things a lot easier on this end.


Silk Screens and Text

I have no equipment for doing silk screens, and I remove text when it is included in the top or bottom layer Gerber files. It wastes time, wears out the mill bits, and generally causes me problems. So don't bother putting text in there because I will delete it.


Traces To Component Pins On The Top Layer

NOT GOOD - Top-layer traces go to relay pins (highlighted
in red) which are covered up when the relay is in place


If you want to run a top-layer trace to a component pin, make sure the pin will be visible from above the board when the component is in place. With our boards, soldering a pin on the bottom will not be sufficient to make a reliable connection to a trace on the top. So it is best to put all traces to these invisible pins on the bottom layer of the board.

If you absolutely must have traces on the top side going to pins obscured by the component (or if you forgot to follow the rules!), it is difficult but possible to solder the component on anyway.


Rubout Areas

Normally, our boards are made with a strip of copper removed around the outside of the traces and pads, and the rest of the copper left on the board, like on our main PCB page. But it's possible for me to remove all the copper on the board except for the traces, pads, etc. This takes longer, but some people need this done, especially if they have transmission lines on the board and the extra copper will cause interference. If you need all the excess copper removed from the board, specify this in your request email. BUT, due to the extra time and bit wear, I am reluctant to do this unless absolutely necessary. The regular channels are wide enough to make it easy to solder DIP and surface mount components down.

Mistakes and Revisions

Very few people make a perfect working PCB on the first try. If there are wiring mistakes in your design, please try to modify the board yourself rather than ordering a new board. Traces can be cut with an XActo knife, and new connections can be made by soldering on jumper wires. If there are only minor problems on the board, please try to correct them this way if at all possible. In the few weeks before demos in Senior Project Lab, I get barraged with large numbers of board orders, and the turnaround time on boards increases. It may be much faster for you to modify the board yourself.


Thanks!
-Mark Smart


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