Nathan Jack wins award for new approach for handling electrostatic discharge
By Shawn Adderly, ECE ILLINOIS
September 15, 2010
- ECE Grad student Nathan Jack recently won him the Best Overall Poster Award at the IEEE International Reliability Physics Symposium.
- His research showed that that it was possible to create a biasing circuit that controlled the gate voltage of the tail transistor during an electrostatic discharge event.
- His results have gained the interest of numerous companies that are looking for ways to make their chip more robust
ECE graduate student Nathan Jack’s novel approach of using current generated by an electrostatic discharge event (ESD) to increase the breakdown voltage of a MOS transistor, won him the Best Overall Poster Award at the IEEE International Reliability Physics Symposium held in Anaheim, California, in May.
Jack’s poster was titled “ESD protection for high-speed receiver circuits,” and was co-authored with ECE Professor Elyse Rosenbaum.
His poster showed that it was possible to create a biasing circuit that controlled the gate voltage of the tail transistor during an ESD event. This in turn allows the source voltage of the input transistor to be adjusted in such a way as to improve reliability of the chip and reduce the need for ESD protection circuits. The approach is the first of its kind.
“Usually integrated circuits have devices to shunt ESD current to protect the chip from being damaged,” Jack said. “In our approach, the ESD current is used to favorably bias circuits in the chip, reducing the need for ESD protection devices.”
It took Jack and Rosenbaum over a year to design, fabricate, and test their chip. In the lab Jack performed tests on two versions of the chip, one with the bias circuit that utilized the ESD current, and one that had a traditional ESD protection circuit.
His tests found that the oxide breakdown voltage in input circuits were affected by the input transistor’s source voltage, noticing a increase in leakage current and decreased gate oxide quality. For his chip that utilized his biasing circuit, he found that the performance of the chip was enhanced. Its performance was not comprised like chips that used ESD protection at the high-speed signal pins of integrated circuits.
“Everyone is looking for a way to make their chip more robust without adding extra capacitance at the input,” Jack said.
This is why there has been plenty of interest in Jack’s findings, with companies looking for ways to make their chip more robust.
“His research is high impact and very practical, by solving problems that industry is facing right now,” Rosenbaum said. “It is applicable to any chip used for high-speed data communications.”
As for the award, Jack said he is pleased to know that the work he’s done has been recognized by academic and industry leaders.
“It is a great addition to further my career,” he said.
Rosenbaum said that she is not surprised by Jack’s success.
“Nathan is a very productive student. He had his first publication his second year as a graduate student,” she said. “He hit the ground running.”
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