Protecting chips and winning Outstanding Paper Awards
By Heather Punke, ECE ILLINOIS
May 28, 2012
- Nathan Jack received the Outstanding Paper Award from the EOS/ESD Symposium held by the Electrostatic Discharge Association.
- His tool, an embeddable "voltage monitor circuit," quantitatively measures the voltage that develops across a transistor should it be zapped by electrostatic discharge.
- Jack developed an interest in this area of research after an internship experience studying electrostatic discharge.
Prior to completing his PhD, ECE graduate student Nathan Jack (MSEE '09, PhD '12) received the Outstanding Paper Award from the EOS/ESD Symposium held by the Electrostatic Discharge Association. His paper presented a new way to measure voltage in a chip when the chip is “zapped” by electrostatic discharge.
Electrostatic discharge (ESD) in integrated circuits is a common occurrence in today’s highly automated manufacturing facilities. Chips are assembled by robots with a lot of moving parts. Those moving parts can transfer or induce static charge on the chips and then inadvertently zap them, Jack explained. “The transistors are so small that even a small amount of static discharge can totally destroy a chip without proper on-chip ESD protection.”
His tool, an embeddable “voltage monitor circuit” presented in the paper, quantitatively measures the voltage that develops across a transistor should it be zapped by electrostatic discharge. “It’s kind of like a tape recorder for voltages that tells you what the stress was inside the chip,” Jack explained. By including these voltage monitor circuits on chips, engineers can learn where chips are vulnerable to damage and how to best protect them.
For this Outstanding Paper Award, all symposium attendees were able to vote in selecting the recipient. Other conference awards were chosen by a committee. “It felt good to receive this level of recognition,” Jack said.
Professor Elyse Rosenbaum, Jack’s adviser, was the co-author of the award winning paper. She said that Jack has three main traits that make him an excellent researcher: persistence, intelligence, and creativity. “Nathan was tenacious. He was also clever. This is why he was ultimately successful on this project,” Rosenbaum said.
Rosenbaum had come up with the idea for this tool about six years ago, but Jack was the one who perfected it and implemented it successfully.
Jack helped to develop the voltage monitor specifically for his PhD research, but published a paper about it for a different reason. “It can also be useful to anyone that is trying to understand the stress that their chip is experiencing,” he explained.
Jack’s interest in ESD reliability and test methods grew after his undergraduate career. “I had an internship the summer just before I came to grad school. I ended up in the ESD reliability group and thought it was pretty fun,” he said. The internship was with Micron Technology in Boise, Idaho, not far from Jack’s Utah home.
The EOS/ESD Symposium is held once a year and is “the international technical forum on electrical overstress and electrostatic discharge,” according to its website. “It is the primary venue for presenting research on the topic of ESD,” Rosenbaum said.
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