Kumar proposes economic models for many-core computing
Lauren Eichmann, ECE Illinois
- Prof. Rakesh Kumar and grad student Joseph Sloan are researching a multi-core chip that allows for customized peak computational capabilities.
- The idea behind the chip is that, in the future, consumers would pay for only the computational capability they use.
- These chips could be mass produced but applicable for a wide variety of applications.
ECE Assistant Professor Rakesh Kumar says he senses computing is becoming increasingly more of a service rather than something that requires ownership. To meet the demands of a society that may be entering the age of processors containing hundreds of cores on the same chip, Kumar and his PhD student, Joseph Sloan, have been researching the realities of a many-core chip that would allow for customized peak computational capabilities.
Based on the idea consumers would use the computational capability they pay for, and conversely pay for what they use, Kumar has proposed four economic models for many-core computing. In today’s market, consumers must predict their target chip capability before making a purchase. Kumar says this proves difficult. "You may end up needing more than what you bought, or you may realize that at some point you bought more than what you needed. Currently, you sort of live with the decision that you make," he says. "You spend some money, you buy a chip, and you hope that it roughly corresponds to your requirements."
With the release of new software, higher computational requirements are often necessary, says Kumar. Alternately, consumers may have purchased a computer or chip amount for a specific purpose, which changes over time.
"If you consider the number of unique chips being manufactured today at the cutting edge of technology, you’ll notice that number is decreasing really fast. Some may find this surprising because people are constantly figuring out new ways to use electronics," says Kumar. "It takes a lot of investment and the risk is high to build a chip on the cutting edge of technology, as the profit margins are low due to stiff competition and high non-recurring engineering (NRE) costs."
Kumar says people ultimately use computers for different purposes. "From the perspective of the vendor, do they really want to make a chip for you and a chip for me? The answer is no."
Thus, one might have to think about alternate economic models, Kumar says. This may be achieved when vendors can enable or disable individual cores in a single processor. It would allow consumers a chance to individualize their computational needs, while decreasing production costs for vendors who will only need to make one standard chip, each with the ability for modification.
An "Upgrades Only" model recognizes that users tend to have increased computational requirements over time. This option would allow consumers to increase the number of cores for their specific processor. Conversely, if a user wants only a temporary adjustment to his computational capability, he may chose the second economic model known as "Limited Up/Downgrade." This allows the user to increase or decrease the core capacity on a provisional basis.
A third model permits consumers to rent computational capabilities from the vendor through a lease, called "CoreOnRent." Unlike the latter two, this model does not involve ownership of cores. Lastly, "PayPerUse" requires the vendor to bill the consumer based on core usage. The four models have been covered in several press articles recently.
"We are engineers. We are computer architects," says Kumar. "We are not economists. The goal is not to come up with the exact economic models or the exact pricing models." Instead, they have merely understood the two pressures that exist: consumer versus vendor-driven incentives. Consumers want the flexibility to go up and down for peak computational ability of the chip, while vendors want to make manufacturing costs low, he says.
Kumar says such economic models themselves are not new. In fact, they exist in several domains, he adds. In the computing domain, for example, mainframe vendors allow their customers - usually high-visibility institutions like Target and Wal-Mart - to use such technology. Through capacity-on-demand (COD), vendors log use and correspondingly generate the bill for the user.
To allow for such models to work for many-core computing, however, mechanisms for chip use enforcement will be necessary. The mechanisms need to ensure that the economic models are honored by the consumer. This has been the primary research focus for Sloan and Kumar. Hardware to prevent users from unlocking additional core usage, or likewise using an increased core capacity for a longer period than which was paid for, is necessary to control, according to Kumar.
Sloan has already designed circuitry that automatically locks chip capability after expiration of contracted use. Another way the vendor can regulate usage is through an authentication of the chip with a physically uncloneable function, known as PUF. This acts as a signature so users cannot tamper with the circuitry log.
Kumar believes that the exact domain in which the technology may be most applicable is unclear and depends on many factors, several of them non-technical. "I think these models would be particularly useful for enterprise computing where smaller anonymous entities are buying more powerful machines," he says. Kumar also acknowledged how desktop users may benefit from many-core computing in the future, but the extent of use may be limited.
Kumar and his student are currently researching hardware support for the models’ authentication and verification. He is also collaborating with pricing and security experts to improve the robustness of such techniques.