Wong awarded grant for lithography-aware physical design research
Katie Carr, Coordinated Science Laboratory
- Professor Martin Wong recently received a three-year, $450,000 National Science Foundation grant to conduct research on lithography-aware physical design.
- Since circuit layout interacts with the lithography process to determine the yield and quality of the microchips, designers must understand the down-stream lithography process, so that the layout patterns generated are printable on silicon.
- The study focuses on the development of electronic design automation (EDA) algorithms and software for lithography-aware physical design
Martin D F Wong, the Edward C. Jordan Professor in Electrical and Computer Engineering, recently received a three-year, $450,000 National Science Foundation grant to conduct research on lithography-aware physical design.
“Today, the most advanced silicon chips have billions of transistors and wire that are tens of miles long on a chip with minimum feature size less than 20 nanometers,” Wong said. “Not too long ago, it was 28nm and 32nm and now they’re talking about sizes like 14, 10 and 7. They keep shrinking while more transistors are getting packed in.”
The challenge is that as the minimum feature size continues to get smaller and become much less than the optical wavelength used in the lithography process, it gets more difficult to manufacture high quality circuitries because of the strong optical interference. The physical design phase generates a circuit layout with detailed locations and geometries of the transistors and wires. Since the circuit layout interact with the lithography process to determine the yield and quality of the microchips, designers must understand the down-stream lithography process, so that the layout patterns generated are printable on silicon.
“Previously, the design was separate from the manufacturing,” Wong said. “The people who design the chips figure out the functionality and how to connect the wires. The designs are then sent to the manufacturer, who takes those specifications and uses masks and excimer lasers to image the circuit.”
Now, with so many possible configurations in the design process and constraints in the manufacturing process, designers need to understand which ones are easier to manufacture and which ones might be more conducive to the lithography process.
In this proposal, Wong will develop electronic design automation (EDA) algorithms and software for lithography-aware physical design. The study will focus on four leading next-generation lithography technologies: triple-patterning lithography (TPL), self-aligned double patterning (SADP), directed self-assembly (DSA) and extreme ultraviolet (EUV).
“As we go from 20nm to 14nm to 10nm, we have to decide exactly what lithography process will be used,” Wong said. “There are various options, so we’re looking at these different strong candidates. I’m going to address issues in chip design so that they will be friendly to a suitable manufacturing process. I plan to look ahead and see how to integrate design with strong candidates for lithography in the future.”
Wong is a researcher at the Coordinated Science Laboratory and acting associate dean for academic affairs in the College of Engineering. He has published over 400 papers at premier EDA journals and conferences and has supervised 43 Ph.D. dissertations in EDA. He has been active in lithography-aware physical design research and recently received the Best Paper Award at 2012 ACM/IEEE Design Automation Conference (DAC) from his paper with Qiang Ma and Hongbo Zhang on “Triple Patterning Aware Routing and its Comparison with Double Pattering Aware Routing in 14nm Technology."