Chen and collaborators receive Best Paper Award at ICCAD
- Professor Deming Chen, along with his graduate students and colleagues from Intel and Ohio State University, recently received the William J. McCalla Best Paper Award at the IEEE/ACM International Conference on Computer Aided Design.
- Chen and his team have proposed an automated design process that targets energy smart SoC designs to create low energy mobile devices that use SoCs for computing and control.
- To deal with these issues, the researchers' unique process generates two different versions of SystemC code - one that creates high level accurate models and another that enables high level synthesis solutions to generate hardware automatically.
Professor Deming Chen, along with his graduate students and colleagues from Intel and Ohio State University, recently received the William J. McCalla Best Paper Award at the IEEE/ACM International Conference on Computer Aided Design. Their paper looks at creating low energy Systems-on-Chips (SoCs) in an automated and efficient manner.
The award is given in memory of McCalla for his contributions to ICCAD and his CAD technical work throughout his career. ICCAD is one of the top conferences in the computer aided design field, where researchers are developing software to help automate design processes for electronic circuits, and the paper was voted as the best paper out of 14 candidates, which were selected from 381 submitted papers.
Chen’s team includes three ECE ILLINOIS graduate students - Wei Zuo, Warren Kemmerer and Jong Bin Lim - as well as Louis-Noël Pouchet, a research assistant professor of computer science and engineering at Ohio State University, and Andrey Ayupov, Taemin Kim and Kyungtae Han from Intel.
As mobile technology is becoming the norm, researchers are looking at ways to save battery power in the devices. Chen and his team have proposed an automated design process that targets energy smart SoC designs to create low energy mobile devices that use SoCs for computing and control.
“Our goal is to minimize the energy consumption up to 10 times and improve the design productivity at the same time,” said Chen, who is also affiliated with the Coordinated Science Laboratory. “To do that, we propose efficient and automated hardware and software design at the same time to create a complete system on one chip.”
Currently, there are many manual aspects to the design process and, Chen said, the design procedures are difficult and labor-intensive. This makes for a lengthy design process and designers end up settling for suboptimal solutions in order to save time. Additionally, the available solutions don’t offer very effective tradeoff options in regards to power versus latency, which is how long it will take to finish a function.
To deal with these issues, the researchers’ unique process generates two different versions of SystemC code – one that creates high level accurate models and another that enables high level synthesis solutions to generate hardware automatically.
The researchers use the SystemC code generation engine, which was primarily developed by Zuo, along with a compilation framework called polyhedral modeling that was developed by Pouchet, to create an analytical model accurately and automatically. This, in turn, speeds up the customized hardware design in the SoC, as well as provides better solutions than previously available.
“The polyhedral model-based compilation framework is very powerful and can provide all kinds of different optimization solutions,” Zuo said. “It also helps us to generate different structures from the source code and can provide important analysis information.”
The framework will help designers choose the optimal balance between latency and power.
“For any given power, we’re looking for the best latency you can get, and for a given latency, we want to know the best power you can achieve,” Kemmerer said. “Ultimately, we prune away anything that is inferior and are left with a curve of optimal points that a designer can then choose from depending on what power or latency they want.”
Based on the analytical model they developed, the researchers can capture the large design space efficiently to then perform design space exploration.
“There are so many options for designing the hardware, so we use our constructed analytical model to explore the options to generate the best tradeoff between latency and power,” Chen said.
This solution can be used by engineers needing to design a lower power SoC quickly. Preliminary results show that their solution is, on average, 2,000 times faster than a baseline method and allows for rapid customized hardware design, which can deliver high performance while consuming much less power.
“Generating this dedicated hardware for SoC is critical, and we want to produce it quickly and optimally, so engineers can achieve their design goals and a device can reach the market in a timely fashion,” Chen said.