Hanumolu's research improves data center energy efficiency

ECE News

Dan Francisco, Integrity Global for SRC
3/30/2015

Story Highlights

  • Associate Professor Pavan Kumar Hanumolu is working to reduce the serial link power consumption, thereby helping data centers and mobile platforms operate more energy efficiently.
  • The research, sponsored by Semiconductor Research Corporation (SRC) through the Texas Analog Center of Excellence (TxACE), was presented last month at the International Solid-State Circuits Conference (ISSCC).
  • The Illinois team designed a 7 gigabit per second transceiver with the first reported on/off embedded clock architecture. The new transceiver achieved an order of magnitude lower serial link power-on compared to existing transceivers

Pavan Kumar  Hanumolu
Pavan Kumar Hanumolu

ECE ILLINOIS researchers are working to reduce the serial link power consumption, thereby helping data centers and mobile platforms operate more energy efficiently.

The research, led by Associate Professor Pavan Kumar Hanumolu andsponsored by Semiconductor Research Corporation (SRC) through the Texas Analog Center of Excellence (TxACE), was presented last month at the International Solid-State Circuits Conference (ISSCC).

Serial links consume about 20 percent of microprocessor power and constitute about 7 percent of overall energy consumption in a data center. These serial links are only sporadically used, such as when there is a request to access a webpage or a miss in the last level of cache.

“It is estimated that serial links are idle more than 50 to 70 percent of the time in many applications, but they still consume nearly all of link’s power even in the idle state,” Hanumolu said. “Our research seeks to reduce microprocessor serial link power consumption by eliminating the serial link idle power component completely.”

As part of the research, the Illinois team designed a 7 gigabit per second transceiver with the first reported on/off embedded clock architecture. The new transceiver achieved an order of magnitude lower serial link power-on compared to existing transceivers.

“The reduction of serial link power consumption not only benefits processors and mobile platforms, but it also reaps continued benefits from Moore’s Law by increasing the computational capacity and off-chip bandwidth for a few more years without adding pressure on the power envelop of the processor,” said Hanumolu, who led the research team that also included PhD student Tejasvi Anand.

Previous technology reports power-on lock times of a couple hundreds of nanoseconds for memory interfaces and a few microseconds in the case of Energy Efficient Ethernet (IEEE 802.3az). The long power-on lock time limits the opportunities of the serial link to save power. The Illinois research reduced the power-on lock time to less than 20 nanoseconds, and this resulted in a 44 times reduction in power.

The Illinois team began the research in 2011 and has reported on multiple advancements over the years, including presenting the new transceiver results at this year’s ISSCC. The team estimates that data centers in North America can save $870 million annually using this approach, with the yearly serial link power savings at data centers worldwide by 2020 equaling Japan’s yearly electricity consumption.

“The conventional way to reduce power is to design and manufacture links on advanced nodes, which can be a costly proposition. The University of Illinois’ approach achieves power savings that should be useful across many technology nodes, and that’s one of the reasons this research is so compelling,” said David Yeh, SRC director of Integrated Circuits and Systems Sciences.

The Illinois transceiver technology can be implemented on any technology node from a manufacturing standpoint, with the research results being demonstrated on 90 and 65 nanometer nodes. The technology can also apply to memory and networking applications.

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